Means for evaluating contact noise utilizing pulse coincidence techniques



May 24, 1966 Filed Dec. 31,

C. C. PACKARD MEANS FOR EVALUATING CONTACT NOISE UTILIZING PULSE COINCIDENCE TECHNIQUES 5 Sheets-Sheet 1 204 205 2oe L EMITTER FOLLOWER m d\/ a Ex fi A T low T- BRUSH SELECTION NETWORK READ OUT COUNTER LATCH ,2" LATCH RESET DELAY V HNTERROGATION 0 y 209 PULSEIGENERATOR as DUAL @416 L INPUT SYNC COUNTER MscoPE LATCH w J on/w 207 GENERATQR INVENTOR.

c. c. PACKARD 7% 14. flax s27 ATTORNEYS May 24, 1966 C C. PACKARD MEANS FOR EVALUATING CONTACT NOISE UTILIZING PULSE COINGIDENGE TECHNIQUES Filed Dec. 51 1959 FIG.3

5 Sheets-Sheet 2 READOUT LATCH I May 24, 1966 c. c. PACKARD 3,253,213

MEANS FOR EVALUATING CONTACT NOISE UTILIZING PULSE COINCIDENCE TECHNIQUES Filed Dec. 31, 1959 5 Sheets-Sheet 5 F l G. 4 +2ov +2ov s CR2 IA B N 406 R7 405 M m +2ov +|ov R9 CR4 CR5 R +|ov RIG May 24, 1966 c. c. PACKARD MEANS FOR EVALUATING CONTACT NOISE UTILIZING PULSE COINCIDENCE] TECHNIQUES 5 Sheets-Sheet 4 Filed Dec. 31, 1959 10:: 5mm: E

y 1955 c. c. PACKARD 3,253,213

MEANS FOR EVALUATING CUNTACT NOISE UTILIZING PULSE COINCIDENCE TECHNIQUES Filed Dec. 31, 1959 5 Sheets-Sheet 5 FIG. 7 NOISE DUE TO VARIATION MOMENTARY m BRUSH CONTACT OPENS RESISTANCE +IOV A. CONVERTER OUTPUT 3 T I +1ov a. RESET DELAY OUTPUT I c SYNC LATCH "o" OUTPUT I D. DELAY PULSE OUTPUT E. TRIGGER LATCH OUTPUT F. PULSE GENERATOR OUTPUT G. INVERTER OUTPUT l. READOUT LATCH OUTPUT United States Patent 3,253,213 MEANS FOR EVALUATING CONTACT NOISE UTILIZING PULSE COINCIDENCE TECH- NIQUES Charles C. Packard, Endicott, N.Y., assignor to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Dec. 31, 1959, Ser. No. 863,306 2 Claims. (Cl. 324-.28)

The present invention relates to apparatus for evaluating contact noise in make and break devices, and more particularly, to means for varying the interrogation time and duration for a brush output from analog-to-digital encoder after a transistion has occurred from a nonconducting segment to a conducting segment.

A typical analog-to-digital brush converter or encoder utilizes a coded disc sensed with stationary brushes to transform analog shaft position information into digital electrical signals. Such a coded disc is usually constructed of several concentric tracks, each of which consists of alternate conducting and nonconducting segments. Each track has associated therewith a brush. At any given shaft position, a brush contacts either a conducting or a nonconducting segment, which provides an ON or an OFF signal level, respectively, from the brush. The number of ON and OFF levels at the read positions defines the shaft angle in accordance with the particular binary code employed.

Encoder failure occurs almost exclusively in the form of incorrect readout signals caused by brush contact noise when a brush is making contact with a conducting segment. Two distinct classifications of noise are present. These are momentary opens caused by brush bounce or particles of nonconducting impurities which accumulate on the conducting segment, and fluctuations in contact resistance of the conducting segment caused by irregularities in the surface or variations in contact pressure. The presence of either of these types of noise may cause an erroneous output signal from the brush, in that an OFF signal level may be indicated even though a conducting segment is beneath the brush. Thermal, thermo-electric, and electrostatic noises are also present, but these noises are not of sufficient magnitude to be considered significant.

Encoder reliability and life span are determined by the extent of brush noise and by certain interrogation parameters. Factors influencing the extent of brush noise include brush pressure, input shaft speed, frequency of brush transitions between segments, and frequency of rotation reversal. Significant interrogation parameters include interrogation pulse width, magnitude of driving voltage and current, and sensitivity of readout equipment. In addition to examining the above quantities, the spatial distribution of noise over a segment must be examined because certain readout techniques avoid interrogation near transition regions.

The present invention is not limited to shaft encoder testing. It may be used directly to investigate the contact noise characteristics of such components as relays, switches, emitters, commutators, or other devices whenever a periodic make and break can be instrumented. With only slight modification of external input equipment, the duration of relay or brush-commutator contact opens during nonperiodic operations may also be measured.

An object of the invention therefore is to provide ap paratus for analyzing a step signal function having first and second levels, which includes first means responsive to said first level of said step signal function for generating an interrogating signal, and second means responsive to said first level together with said interrogating signal for producing an output signal.

3,253,213 Patented May 24, 1966 ice Another object of the present invention is to provide apparatus for determining the location and magnitude of noise generated when a brush contacts a conducting segment on the encoder disc which might otherwise present a successful interrogation of this conducting segment and so give an erroneous indication as to the position of the shaft.

A yet further object of the invention is to provide apparatus in which the initiation of the interrogating signal for a brush is delayed for a certain length of time after the transition has been made from a nonconducting segment to a conducting segment.

Another object of the present invention is to provide means for varying the duration of the interrogating signal which samples the brush readout.

Another object of the invention is to provide a first counting means for counting the number of successful interrogations, represented on ON signal levels, and another counting means for counting the number of total interrogations, so that the accumulative count within the first and second counters represents a ratio of the reliability of the source of step voltage function.

Other objects and features of the invention will be pointed out in the following description which is to be taken with the accompanying drawings, in which:

FIGURE 1 shows a typical analog-to-digital encoder disc and its brushes utilizing a pure binary readout;

FIGURE 2 shows a block diagram of the invention;

FIGURE 3 shows the brush excitation and isolation amplifier;

FIGURE 4 shows the sync latch and reset generator;

FIGURE 5 shows the details of the relay generator;

FIGURE 6 shows the gating and readout circuitry; and

FIGURE 7 shows typical wave forms generated within the circuit of the invention.

Referring first to FIGURE 1, there is shown a typical coded disc which may be used in an analog-to-di-gital brush encoder having a pure binary output. Disc 101 has thereon a plurality of concentric circular tracks, with each track composed of conducting segments 103 denoted by shaded portions and nonconducting segments 102 denoted by light portions. In the pure binary system, the outermost of the concentric tracks will contain twice as many conducting and nonconducting segments as does the next adjacent track. This ratio continues as progress is made toward the center of the disc. Associated with the concentric tracks are a plurality of readout brushes 105,

Y 106, 107, and 108, there being one brush for each track.

These brushes may be arranged on a common read line 104, or they may be staggered on different radii of the disc. A common brush 109 is associated with the innermost concentric track which is completely conducting, and it is connected to a ground return path. Since all of the conducting segments 103 on the disc make contact, either directly or indirectly with this innermost grounded track, then these segments are also at ground potential. Each brush reads a different concentric circle, so it is seen that brush 105 indicates the value of the 2 binary bit of the binary number representing the analog position of the shaft. Brush 106 indicates the 2 binary bit of this number, and so forth. If a brush contacts a conducting segment, then it is approximately at ground potential and thus indicates that its bit has a 1 value. For conveniencesake, the readout lines from these four brushes are tied together in a cable 110 which is connected to the brush selection net-work 205 shown in FIGURE 2, along with the cables from the other converters which are also on the motor shaft.

Turning now to FIGURE 2, a plurality of converters under investigation are mounted in a test fixture 202 where they are driven in common by a variable speed direct current motor 201. The motor field current may be applied through a timing circuit, not shown, that provides a periodic reversal of rotation so that interrogations can be conducted with the coded disc revolving in opposite directions. Each converter has a plurality of brushes associated therewith, as more particularly shown in FIGURE 1, and the particular converter and a particular brush thereon to be tested is selected by a switching network 205, the details of which are not shown. Cable 203 represents the brush outputs from one converter. Brush excitation circuit 206 provides substantially a two-level ON and OFF step signal function output, depending upon whether the brush under test is contacting a nonconducting segment or a conducting segment on its associated coded disc. Upon the brush making a transition from a nonconducting segment to a conducting segment, the output signal from unit 206 will change from an OFF level magnitude to an ON level magnitude and remain at said ON level, except for the presence of brush noise, until the brush again makes contact with a nonconducting segment. Upon the brush making a transition from a nonconducting segment to a conducting segment, a sync latch 207 will be set to an ON condition by the ON level from 206, and upon the brush making a transition from the conducting segment back to a nonconducting segment, the sync latch will be reset to an OFF condition by reset delay 208 which receives the OFF level output signal from unit 206. When latch circuit 207 is initially set to its ON condition, a signal is applied to delay generator 209 which will subsequently, with a variable time delay, produce a pulse applied to interrogation pulse generator 210. Upon receipt of this pulse from delay generator 209, interrogation pulse generator 210 generates an interrogation signal whose duration is varied according to the requirements of the test. This interrogation signal is applied through inverter 211 to one input of AND circuit 212. The other input of AND circuit 212 is derived from the output of unit 206. An output from AND circuit 212 is obtained whenever there is present at its inputs the interrogation signal together with the ON level signal from unit 206. If the output of AND circuit 212 is present for a certain minimum duration, this causes readout latch 213 to be set to an ON condition. The readout latch 213 is reset to an OFF condition upon the termination of the interrogation signal from generator 210.

Connected to the output of readout latch 213 is a first counter 214 which is actuated in response to latch 213 being set to its ON condition. Also connected to the output of pulse generator 210 is a second counter 215 which is actuated in response to the interrogation signal. Each counter is incremented by a count of 1 at the time that its associated input signal initially appears. Counter 215 therefore records the total number of interrogation signals which are generated during the time that the brush is tested, while counter 214 records the number of successful interrogations of the brush as determined by the presence of an ON signal level from unit 206 sometime during the interrogation. Counter 215 may be used to turn counter 214 on and off at some convenient reference such as 1,000 or 10,000 counts, thus providing a direct reading of percent successful interrogations at counter 214. The converter output from unit 206 and the interrogation signal from generator 210 may be monitored simultaneously on a dual input oscilloscope 216 to facilitate setting up the desired interrogation signal width and delay. Scope 216 is synchronized from sync latch 207 which provides a common reference.

The range of delay provided by delay generator 209, and the range of interrogation signal width provided by pulse generator 210, must be sufficiently large to allow any portion of a conducting segment to be sampled over a reasonable spread of noise conditions. In the present embodiment, signal width may be varied from 1 to 10,000

4 microseconds and delayed up to 4 seconds from the time that a brush crosses a transition point.

Turning now to FIGURE 3, there is shown the circuit of the brush excitation and isolation amplifier 206 of FIGURE 2. Lead 301 may be selectively coupled to any one of the brushes on any one of the converters by means of brush selection network 205. TR is a P-N-P transis tor used as an emitter follower amplifier having emitter 302, base 304, and collector 303. Base current limiting resistor R is connected to lead 301 with a speed-up capacitor C connected in parallel therewith. Emitter load resistor R is connected to a +20 volt potential, while fixed resistor R and variable resistor R are connected in series and connected between the lead 301 and the +20 volt potential which provides brush excitation current. Diode CR clamps lead 301 to a maximum potential of +10 volts. Output lead 305 is taken from emitter 302 and connected to lead 401 in FIGURE 4, subsequently to be described.

The operation of FIGURE 3 will now be described with particular reference to the waveforms of FIGURE 7, wherein .the identifying letter associated with each signal corresponds to the point at which the signal is observed. When the converter brush being tested is contacting a nonconducting segment on the coded disc, then an open circuit exists between conductor 301 and the common ground return path. With the +20 volt potential applied to the series combination of resistors R and R the potential at point A is limited to a maximum of 10 volts due to the presence of diode CR Due to the small value of resistor R the potential of base 304 of transistor TR is but slightly above this 10 volt potential. Therefore, inasmuch as TR is a P-N-P transistor, it will be in a conducting state since base 304 is lower in potential than emitter 302 which is connected through resistor R to +20 volts. The potential of emitter 302 at this time for all practical purposes may be considered to be approximately 10 volts, or slightly above the potential of base 304. This potential represents the OFF level of the brush.

When a transition is made by the brush so as to contact a conducting segment on the coded disc, then point A falls to essentially ground potential due to the completion of the circuit. Brush current at this time may be varied from one to ten milliamps by adjustment of R Upon the reduction of potential at point A, a negative spike is transferred across the speedup capacitor C so as to quickly reduce the potential at base 304 of transistor TR Consequently, more current flows from the emitter to the collector and the potential of emitter 304 is reduced accordingly so as to approach ground potential. This low potential from emitter 304 represents the ON level of the brush.

Thus, the output of amplifier TR will essentially follow the potential of the brush to which lead 301 is connected. In an ideal converter, the potential at point A would be maintained at ground potential level when the brush is in contact with a conducting segment. However, as before noted, the brush may bounce or there may he opens in the conducting segment which would momentarily cause the potential at point A to climb to +10 volts. Furthermore, the contact resistance of the conducting segment may vary as the brush traverses its length so that grass noise appears at point A. These different types of noise are shown in FIGURE 7. The potential at emitter 302 also reflects this noise by increasing. Upon the brush again making a transition from a conducting segment to a nonconducting segment, the potential at point A will rise to +10 volts. Normally, nonconducting segments are noise free with negligible exception, so that this +10 volt potential is uninterrupted.

Referring now to FIGURE 4, the sync latch and reset delay circuits will be described. These circuits are represented by blocks 207 and 208, respectively, in FIGURE 2. P-N-P transistors TR, and TR are cross coupled so as to form the bistable sync latch having an ON condition and an OFF condition. The sync latch is in its OFF condition during the time that the brush contacts a nonconducting segment, which is defined by the fact that transistor TR is conducting while transistor TR is not conducting. Conversely, the sync latch is triggered to its ON condition when the brush makes a transition from a nonconducting segment to a conducting segment and remains in this ON condition until the brush returns to a nonconducting segment. The ON condition is indicated by transistor TR, conducting while transistor TR is not conducting. The latch is triggered to its ON condition by a drop in potential appearing on input lead 401 which is taken from emitter 302 of transistor TR in FIGURE 3, while the latch is triggered to its OFF condition by a drop in potential appearing on base 406 of transistor TR in the reset generator of FIGURE 4.

In the sync latch, a voltage divider circuit consisting of resistors R R R and diode CR is connected between the +20 volt terminal and collector 409 of transistor TR Base 413 of transistor TR is connected between resistors R and R of this voltage divider. In like fashion, a voltage divider consisting of resistors R R R and diode CR is connected across the +20 volt terminal and collector 412 of transistor TR Base 410 of transistor TR is connected between resistors R and R of this second voltage divider. Collectors 412 and 409 are connected to +20 volt terminals through respective load resistors R and R Furthermore, diodes CR and CR clamp collectors 412 and 409 respectively, so that their potential cannot drop below ground. Diodes CR and CR which are connected between the collectors and the voltage dividers, limit the collector current of their associated transistors when in the conducting state.

Capacitors 0., and C are connected so as to speed up the turning on and turning off of transistor TR Capacitors C and G are similarly used to speed up the turning on and turning off of transistor TR Diode GR, is connected to base 410 transistor TR through capacitor C and is poled so as to transmit a drop in potential on input 401 which sets the sync latch to its ON condition. In like fashion, diode CR is connected through capacitor C to the base 413 of transistor TR and is poled so as to allow a drop in potential at point B (at the base 406 of transistor TR to reset the sync latch to its OFF condition. Output lead 415 from collector 412 is directed to the delay generator 209 of FIGURES 2 and 5, while output lead 414 from collector 409 may be directed to the sync input of the oscilloscope 216 shown in FIGURE 2.

The circuit consisting of transistors TR and TR provides a reset delay for the sync latch which causes the latch to be reset to its OFF condition a certain time after the brush makes a transition from a conducting segment to a nonconducting segment. The input from FIGURE 3 applied to lead 401 is directed to base 402 of transistor TR through current limiting resistor R and speedup capacitor C Emitter 403 is connected through load resistor R to the +20 volt terminal, while collector 404 is grounded. TR is therefore an emitter follower. The output from emitter 403 is directed to an R-C circuit consisting of variable resistor R and capactor C Transistor TR is a silicon unijunction transistor whose emitter 405 is connected to the junction between R and C Its operation is similar to that of a thyratron. When the potential across capacitor C reaches a critical positive potential, TR fires and capacitor C discharges through emitter 405 to base 407. This action is accompanied by a current flow from base 406 to base 407 which results in a drop of potential at base 406. Diode CR is connected between base 405 of transistor TR and collector 409 of transistor TR, in the sync latch. Its function is to prevent continuous firing of transistor TR after the sync latch has once been reset to its OFF condition. Diode CR is connected in parallel with resistor R and poled in a direction so as to provide a rapid discharge path for capacitor C 6 whenever the potential drops at emitter 403 of transistor TR The operation of the sync latch and its reset delay circuit will now be described. When the brush makes contact with a nonconducting segment, the potential at input lead 401 is approximately ten volts. Sync latch is also in its OFF condition which means that transistor TR is conducting while transistor TR is nonconducting. In the transition from a nonconducting segment to a conducting segment, the potential of emitter 302 in FIGURE 3 drops to a point close to ground, which thereupon directs a negative pulse through diode CR and capacitor C to base 410 of transistor TR This causes base 410 to drop below the potential of emitter 408 so as to render transistor TR conducting. Current flow in collector 409 now causes its potential to rise so as to transmit a positive pulse through capacitor C in order to raise base 413 of transistor TR above the potential of emitter 411. This causes transistor TR to cease conducting which thus drops its collector potential to ground. Since there is now a voltage drop of 20 volts across the voltage divider circuit connected to base 410 of transistor "PR said base is maintained at a potential lower than that of its emitter 408 so as to continue conduction therethrough. How ever, since the potential of collector 409 is now higher than ground, the potential at base 413 of transistor TR remains higher than its emitter 411 so as to maintain it in a nonconducting state. The sync latch is now in its ON state and will remain therein until a negative reset pulse arrives at base 413 of TR During the time that transistor TR in FIGURE 3 is conducting heavily, the potential on lead 401 is close to ground so as to render TR heavily conducting. This drops the potential at emitter 403 below the firing voltage of transistor TR However, when brush noise is present, or upon transition of the brush from a conducting segment to a nonconducting segment, the voltage at lead 401 again rises which renders transistor TR less conducting and thus raises the potential at its emitter 403. Since capacitor C charges through resistor R however, a certain time delay will occur before its potential can pos sibly reach the firing voltage of transistor TR Upon reaching this firing potential, a drop in potential is produced at point B which is coupled through diode CR and capacitor C to base 413 of transistor TR This negative pulse switches on transistor TR which thus causes transistor TR to be turned off. Capacitor C also discharges through transistor TR which eventually ceases conduction when the potential at its base 406 reaches an extinguishing value. Since diode CR has its cathode connected to collector 409 of transistor TR it is seen that emitter 405 of transistor TR cannot thereafter rise to its firing potential since collector 409 is at ground potential when the sync latch is in its OFF condition.

The reset delay circuit is required so as to prevent erroneous reset of the sync latch in case any noise pulses of sufficient magnitude are detected by the brush while on the conducting segment. In other words, it is desired to reset the sync latch only when a transition is made from a conducting segment to a nonconducting segment. However, each such noise pulse causes the potential at emitter 403 to momentarily rise and so begin charging C Diode CR is poled so as to bypass resistor R and allow the rapid discharge of capacitor C when emitter 403 falls again so as to completely remove any charge which might be built up from these noise pulses. Otherwise, a quick succession of noise pulses might cause an accumulation of charge which eventually would reach the firing potential of TR and thus cause the reset of the sync latch while the brush is on the conductive segment. In such case, the sync latch might well be set again to its ON condition more than once during each conducting segment.

Referring now to FIGURE 5, the circuit of delay generator 209 of FIGURE 2 will now be described. Interrogation delays of from 0.2 microsecond to 4 seconds are provided therein in three continuous ranges as selected by variable resistor R and switches S S and S Switches S S and S are mechanically ganged together, and provide the coarse delay adjustment. Up to 500 microseconds delay is available when these switches are in their first position, while delays of 500 microseconds to 40 milliseconds are available when they are in their second position. Delays up to 4 seconds may be obtained when they are in their third position. Resistor R provides the fine delay adjustment within each of these three ranges.

TR is an N-P-N transistor having its base 503 coupled between resistors R and R of a voltage divider cornprising resistors R R and R in series. One terminal of the voltage divider is connected to input lead 504 which is coupled to output lead 415 of the sync latch in FIG URE 4. The other terminal of this voltage divider is coupled to a 20 volt potential. Speedup capacitor C is connected across resistors R and R so as to speed up the effect of any change in potential at input lead 504. Collector 501 is coupled through load resistor R to a +20 volt terminal and is clamped through diode CR to a maximum of volts. Emitter 502 is coupled to a 6 volt terminal. Diode CR is coupled between collector 501 and one terminal of resistor R17 and is poled so as to limit the current flow in collector circuit in order to protect transistor TR The output from collector 501 is coupled to variable resistor R the other terminal of which is connected to the rotating contact of switch S Resistor R is connected between collector 501 and the 1 contact of switch S The purpose of resistor R is to reduce the effective resistance of R when switch S is in its 1 position so that R can be manipulated through its entire range. The 1 contact of switch S A is connected to one terminal of a charging circuit consisting of resistor R and capacitor C whose other terminal is connected to the volt terminal. Across the charging circuit is connected resistor R N-P-N transistor TR; has its base 507 coupled to one terminal of resistor R through current limiting resistors R and R Furthermore, base 507 is coupled through clamping diode CR to collector 501 of transistor TR Collector 506 is coupled through load resistor R to the +20 volt terminal and is clamped to a maximum of ten volts through diode CR Emitter 505 is grounded. Protection diode CR is coupled between one terminal of resistor R and collector 506 so as to limit the current flow through collector 506.

Contacts 2 and 3 of switch S are both connected to a charging circuit consisting of resistor R and capacitor C Transistor TR is a silicon unijunction transistor, similar to TR in FIGURE 4, having its emitter 508 connected to one side of capacitor C as shown. Furthermore, emitter 508 is connected to collector 501 of transistor TR through diode CR poled in the direction shown. Base 510 is connected through load resistor R to the +20 volt terminal, while the other base 509 is connected to the --6 volt terminal. The output of base 510 is connected to the 2 contact of switch S and also to the moving contact of switch S Contact 3 of switch S is connected through base current limiting resistor R to base 511 of P-NP transistor TR Emitter 513 is connected through load resistor R to the +20 volt terminal, and is also connected to one terminal of resistor R Collector 512 is connected to the --6 volt terminal. Resistor R capacitor C resistor R and capacitor C are connected in series in this order with the other terminal of capacitor C being connected to the +6 volt terminal. Diode CR is connected in parallel with resistor R and capacitor C Transistor TR together with its above-described resistors, capacitors, and diode, forms a frequency dividing or counting circuit in which increments of charge are periodically transferred from capacitor C to capacitor C in order to gradually increase the potential at the emitter 514 of transistor TR TR is a silicon unijunction transistor having its emitter 514 connected between capacitor C and resistor R Furthermore, clamping diode CR is connected between emitter 514 and collector 1 of transistor TR Base 516 is connected through load resistor R to the +20 volt terminal and is further connected to contact 3 of switch S The moving contact of switch S is connected to output lead 519 which is directed to trigger latch 517. This trigger latch 517 is identical to the sync latch shown in FIGURE 4. Lead 519 is connected to an input corresponding to input 401 in FIGURE 4. Collector 501 of transistor TR is also connected to output lead 520 which in turn is connected to the cathode of a diode corresponding to CR in FIG URE 4 so as to reset trigger latch 517 to its OFF condition when the potential drops at collector 501. Diode CR is connected between emitter 508 of transistor T11 and the collector of a transistor in trigger latch 517 which is nonconducting when the latch is set to its ON condition. Such a transistor corresponds to transistor TR in the sync latch whose collector stands at ground potential when the sync latch is in ON condition. The purpose of diode CR is to prevent a firing potential from being impressed on emitter 508 while latch 517 is ON.

The operation of FIGURE 5 will now be described, with particular reference to the waveforms at points D and E shown in FIGURE 7. When a brush is contacting a nonconducting segment, the sync latch of FIGURE 4 will be in its OFF condition so that output lead 416 is raised substantially above ground potential. In such case, base 5'03 of transistor TR is at a potential so as to cause it to heavily conduct. Therefore, the potential of collector 501 is quite low due to the current flow through resistor R This low potential of collector 501 is transmitted through diode CR to base 507 of transistor TR so as to prevent current flow therethrough. Collector 506, however, is clamped at +10 volts and cannot rise above this value. If it is assumed at this time that switches S and S are in their 1 positions, then this 10 volt potential is applied to trigger latch 517 via lead 519. Upon the sync latch being set to its ON condition by the brush transition, the potential at lead 504 will drop to approximately ground so as to reduce the current flow in collecor circuit 501 of transistor TR The potential at collector 501 thereby increases to its maximum of 10 volts. Still assuming that switch S is on contact 1, capacitor C is charged through resistor R which is serially connected to the parallel combination of resistors R and R Depending upon the particular setting of resistor R the potential at base 507 of transistor TR7 will rise so that it will be turned ON at some time delayed from the appearance of +10 volts on collector 50 1 of TR The drop in potential at collector 506 is sent to trigger latch 517 so as to set it to its ON condition. As mentioned before, with this setting of switches S and S resistor R can be varied so as to provide delays up to 500 microseconds.

Now assuming that switches S and 8 are resting on their 2 contacts, it is seen that capacitor C is instead charged through resistors R and R when the potential at collector 501 increases. It should be noted that while TR is heavily conducting, emitter 508 of transistor TRg is kept at low potential through diode CR However, upon the potential at collector 5021 increasing, the firing potential of transistor TRg is eventually reached at emitter 508 at a time delay dependent upon the setting of resistor R The value of R and C coupled with the fact that R is no longer in parallel with R allows the firing of TR to be delayed from 500 microseconds to 40 milliseconds. A drop in potential is generated at base 510 which is transmitted through contact 2 of switch S so as to set trigger latch 517 to its ON condition. After the trigger latch has been set to its ON condition, diode CR will clamp emitter 508 at ground potential so as to prevent TR from acting as an oscillator due to the continued presence of high potential at collector 501.

If delays of from 40 milliseconds to 4 seconds are desired, the switches are set to their 3 contact. This allows the output from transistor TR to be directed to base 511 of transistor TRg instead of to output line 519. When TR is not conducting, base 511 of transistor TR is at a potential high enough so as to prevent conduction of transistor TR It is now again assumed that the collector potential of transistor TR is low due to the fact that the brush is on a nonconducting segment. Therefore, the potential at emitter 514 of transistor TR is also low since diode CR clamps it to collector 501. Transistor TR cannot possibly fire at this time. Also at this time it is noted that the voltage across capacitor C is small due to the fact that one of its terminals is clamped to the 6 volt terminal, while the other terminal is connected through resistor R to base 514. However, capacitor C has a large potential thereacross since one terminal is clamped to the +20 volt terminal through resistors R and R and transistor TR is not conducting.

Upon a brush transition from a nonconducting to a conducting segment, the potential in collector 501 increases so as to cause transistor TR to fire shortly thereafter, as has been previously described. With the drop in potential at base 510, transistor TR becomes conducting so as to drop the potential at emitter 51 3'. Thereupon, capacitors C and C begin to discharge since the total voltage potential across them is now reduced due to current flow through TR via R However, diode CR is poled so as to effectively short circuit the series circuit of R and C thus substantially reducing the time constant of the discharge path for C However, C must still discharge through R and R Therefore, capacitor C is discharged at a much faster rate than is capacitor C Eventually, the current flow through TR is extinguished which raises the base potential of transistor TR so as to turn it OFF. Capacitors C and C now begin to charge at the same rate due to the rise in potential across them. Diode CR is now reverse biased and a charging path is completed from the +20 volt terminal through R31, R32, C R 3, and C The values of these resistors and capacitors are so proportioned that a greater charge is placed back onto capacitor C during the duration of this charging time than was lost during the discharge time. Therefore, the potential on emitter 514 is incrementally increased.

Transistor TR will act as an oscillator as long as the potential at collector 501 is high and as long as trigger latch 517 is OFF. This is because capacitor C discharges upon the firing of TR,;. When TR is extinguished, then C again charges to the firing potential, and so the operation is repeated. Therefore, the above-described charging time of capacitors C and C is interrupted by another firing of TR The second drop in potential at base 510 will again cause transistor TR to conduct, thus causing capacitor C to discharge rapidly while hardly discharging capacitor C at all. Upon cessation of conduction through TR another incremental charge will be added to capacitor C Thus, with each input pulse from TR to the base of transistor TR there will be in incremental increase of potential at emitter 5114 of transistor TR which will eventually result in its firing potential being reached. After a certain number of pulses from TR transistor TR will therefore tire and cause a drop in potential to appear on output lead 519 which will set trigger 517 to its ON condition. C discharges through TR but cannot thereafter charge again to the firing potential since transistor TR is no longer operating due to clamping diode CR When transistor TR is returned to its heavily conducting state because of a brush transition from a conducting to a nonconducting segment, the drop in potential at collector 501 resets trigger latch 517 to its OFF condition.

Trigger latch 517, when set on its ON condition pro- 10 vides a positive pulse on output lead 518 for triggering the interrogation pulse generator 210 shown in block form in FIGURE 2. Such a generator may be similar to the Tektronix Pulse Generator, type 163, which provides a positive output pulse of adjustable width. This adjustable width interrogation signal is fed, among other places, to

inverter 211 of FIGURE 2, which is shown in greater detail, along with AND circuit 212, in FIGURE 6.

In FIGURE 6, the positive interrogation signal from the interrogation pulse generator is applied at input lead 601. A voltage divider IIC ZWOIk consisting of resistors R35, R and R37 is connected between lead 601 and ground, together with speedup capacitor C connected across resistors R and R Base 607 of N-P-N transistor TR is connected to one terminal of resistor R Its emitter 606 is grounded. Cfllect-or 605 is coupled to the +20 volt terminal through 1 )ad resistor R Diode CR is coupled between collector 605 and a point on the voltage divider so as to limit collector current. Collector 605 is also clamped to a maximum +10 volt potential through diode CR TR therefore inverts the signal applied at 601.

Diodes CR and CR coupled with resistor R are used as a negative AND gate. The input to diode CR is coupled to collector 605, while the input to diode CR is coupled to input lead 609. Input lead 609 is connected to output lead 305 in FIGURE 3. The ouput 603 of this AND gate, corresponding to unit 212 in FIGURE 2, is directed to the set input of the readout latch 213 whose construction is identical with the sync latch shown in FIG- URE 4. Lead 601 is also coupled to the reset input of readout latch 2 13 via lead 602. Resistor R is coupled to the '6 volt terminal. The circuit para-meters of readout latch 213 are so chosen that a signal appearing on its set lead 603 must be within 30 percent of its down level, for at least 0.5 microsecond, in order to set it to its ON condition. However, if a different latch sensitivity is desired, the simple addition of a divider network to the set input allows the readout latch 213 to change state for any particular level of input signal. Once'readout latch 2113 has been set to its ON condition, it will remain in this state until it is reset to its OFLF condition by the trailing edge of the interrogation signal.

The operation of FIGURE 6 will now be described with particular reference to the waveforms at points F, G, H, and I. In the absence of a pulse from interrogation pulse generator 210, the potential of lead 601 will be down so as to cause little or no conduction through transistor TR Therefore, the potential at collector 605 is at its maximum 10 volts which is transferred through diode CR and appears on the set lead 603. When the interrogation signal appears at input 601, and for the duration thereof, base 607 of transistor TR is increased in potential so as to initiate a heavy conduction therethrough. Therefore, the potential of collector 605 decreases. If the output of transistor TR in FIGURE 3 is also down at any time during the presence of the interrogation signal, then the potential of lead 603 will also be down, since the potential at point H follows the higher of the two voltages applied at the inputs of diodes C-R and OR However, readout latch 213 will not be set to its ON condition unless the signal on lead 603 is within 30 percent of the down level for at least 0.5 microsecond as before described. Since the input to diode CR is derived from the converter brush output by way of transistor TR it is seen that the signal at point H will essentially follow the converter brush output during the interrogation time. An interrogation is therefore not considered successful until the converter brush signal is at a certain level for a certain length of time. In other words, contact noise must be below a certain minimum in order that the readout circuitry can detect the binary l indication of a brush when on a conducting segment.

The leading edge of the ON signal from readout latch 214 is applied via lead 608 to counter 214 in FIGURE 2 in order to record the number of successful interrogations. Latch 213 can only be turned on once, if at all, during each interrogation signal time. As noted previously, counter 215 in FIGURE 2 counts the number of total interrogations as determined from the number of interrogation pulses supplied by generator 210. Suitable counters for this purpose may be the Berkely Universal Eput and Timer Model 73600. After a certain predetermined count in counter 215, an output therefrom may be used to prevent the further addition of pulses to counter 214 so as to directly indicate the percent of successful interrogations.

The following values for the components shown in FIGURES 3 to 6 are exemplary of a preferred embodiment. However, they are not to be construed as limiting the invention to the particular values indicated in the following table. All resistances are in terms of ohms.

R 2K R 51K R 201 R 250K R 1K R 100K R 1K R 5.1K R 1K R 5.1K R 2K R 510 R 250K R 5.6K R 1K R 2K R 20K R 2K R 470 R 1K R 7.5K R 2K R 7.5K R 400 13 470 R 5.1K R 20K R 2K R 5.6K 35 22K R 5.6K R 2.2K R K R 5.1K

a R K R 7.5K R 2K C mmf. 390 C mmf. 330 C n1mf. 390 C mf. .01 C mf. .05 C mf. .25 C mmf. 51 C mf. .1 C mmf. 100 C mf. .5 C rnrnf. 51 C rnmf. 10 C mmf. 100

In the above preferred embodiment, transistors TR T R TR TR and TR may be of the type known as 2N123. Transistors TR TR and TR may be of the type known as 2N490. Transistors TR TRq, and TR may be of the type known as IBM 51. Diodes CR through CR may be of the type known as 1N19l.

Although the invention has been described with reference to a preferred embodiment, it will be understood that many modifications and changes therein will occur to those skilled in the art without departing from the spirit of the invention. Accordingly, the scope of the 12 invention is not intended to be limited except as defined by the following claims.

What is claimed is:

1. Apparatus for analyzing contact noise in brush encoders, said encoders having conducting and non-conducting segments, said noise being produced, if at all, during brush contact with said conducting segments, which includes means for producing a step signal function having first and second levels, representative respectively of conducting and non-conducting segments of said encoders, a first latch set to a first condition in response to said first level and reset to a second condition in response to said second level, means responsive to said first condition of said first latch for producing a delayed signal, means responsive to said delayed signal for generating an interrogation signal of variable duration, means responsive to said first level together with said interrogation signal for producing an output signal representative of said first level during the period of said interrogation signal, means to compare said output signal with a predetermined standard, means to count the number of signals meeting said standard to obtain a first count, means to obtain a second count indicative of said interrogation signals responsible for said output signals and means to compare said first and second signals to provide said analysis.

2. Apparatus for analyzing a step function having first and second levels which includes first means being set to a first condition in response to each change in said step signal function from said second level to said first level, second means responsive to said first condition for generating an interrogation signal a predetermined time after said change, third means responsive to said first level together with said interrogating signal for producing an output signal representative of said first level during the period of said interrogation signal, means to compare said output signal with a predetermined standard, means to count the number of output signals meeting said standard to obtain the first count, means to obtain the second count indicative of said interrogation signals responsible for said output signals and means to compare said first and second counts to provide said analysis.

References Cited by the Examiner UNITED STATES PATENTS 2,418,424 4/1947 Plym 324-28 2,432,944 12/1947 Shillington 324-28 2,828,465 3/1958 Morton 324-28 2,857,531 10/1958 Altieri 324-63 2,877,413 3/1959 Mueblner 32468 2,904,752 9/1959 Perzley 324-68 2,939,075 5/1960 Schwab 32457 WALTER L. CARLSON, Primary Examiner.

SAMUEL BERNSTEIN, Examiner.

G. L. LETT, Assistant Examiner. 

1. APPARATUS FOR ANALYZING CONTACT NOISE IN BRUSH ENCODERS, SAID ENCODERS HAVING CONDUCTING AND NON-CONDUCTING SEGMENTS, SAID NOISE BEING PRODUCED, IF AT ALL, DURING BRUSH CONTACT WITH SAID CONDUCTING SEGMENTS, WHICH INCLUDES MEANS FOR PRODUCING A STEP SIGNAL FUNCTION HAVING FIRST AND SECOND LEVELS, REPRESENTATIVE RESPECTIVELY OF CONDUCTING AND NON-CONDUCTING SEGMENTS OF SAID ENCODERS, A FIRST LATCH SET FOR A FIRST CONDITION IN RESPONSE TO SAID FIRST LEVEL AND RESET TO A SECOND CONDITION IN RESPONSE TO SAID SECOND LEVEL, MEANS RESPONSIVE TO SAID FIRST CONDITION OF SAID FIRST LATCH FOR PRODUCING A DELAYED SIGNAL, MEANS RESPONSIVE TO SAID DELAYED SIGNAL FOR GENERATING AN 